Radio transceiver on a chip

ABSTRACT

An entire radio transceiver can be completely integrated into one IC chip. In order to integrate the IF filters on the chip, a heterodyne architecture with a low IF is used. A single, directly modulated VCO is used for both up-conversion during transmission, and down-conversion during reception. Bond-wires are used as resonators in the oscillator tank for the VCO. A TDD scheme is used in the air interface to eliminate cross-talk or leakage. A Gaussian-shaped binary FSK modulation scheme is used to provide a number of other implementation advantages.

This application is a Continuation of, and incorporates by reference theentire disclosure of, U.S. patent application Ser. No. 08/803,392 filedFeb. 20, 1997 now U.S. Pat. No. 6,633,550.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The present invention relates in general to the wireless communicationsfield and, in particular, to a short-range radio transceiver fabricatedon an integrated circuit chip.

2. Description of Related Art

The high level of circuit integration possible with modern technologyhas allowed manufacturers of hand-held communications equipment (e.g.,cellular phones) to substantially reduce the size of their products. Asa general rule, these smaller products consume less power and ultimatelybecome cheaper to produce.

In the past, there have been a number of attempts to fabricate an entireradio transmitter/receiver (transceiver) on a single integrated circuit(IC) chip. Generally, these attempts have been unsuccessful, and onlyparts of such radios have been placed on a single chip. For example,U.S. Pat. No. 5,428,835 to Okanobu discloses a receiver circuit formedon a single semiconductor chip. The primary reason for this lack oftotal integration can be found in the radio system specifications.

Most standard air interface specifications for radio communicationssystems set forth high requirements with respect to frequency accuracy,adjacent channel interference, modulation performance, etc. However,existing on-chip signal processing techniques have not yet reached alevel that can meet the performance criteria set by these air interfacespecifications.

SUMMARY OF THE INVENTION

It is an object of the present invention to significantly reduce theoverall size of a radio transceiver.

It is another object of the present invention to produce a short-rangewireless radio link that is less costly than a cable link.

It is yet another object of the present invention to produce ashort-range radio transceiver on a single integrated circuit chip.

In accordance with the present invention, the foregoing and otherobjects are achieved by a radio transceiver architecture that can becompletely integrated into one semiconductor IC chip. In order tointegrate the transceiver's IF filters into the chip, a heterodynearchitecture with a relatively low IF is used. A single directlymodulated VCO is used for both up-conversion during transmission, anddown-conversion during reception. Bondwires are used as resonators inthe oscillator tank for the VCO. A time-division duplex scheme is usedin the air interface to eliminate cross-talk or leakage. AGaussian-shaped binary FSK modulation scheme is used to provide a numberof other implementation advantages.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the method and apparatus of the presentinvention may be had by reference to the following detailed descriptionwhen taken in conjunction with the accompanying drawings wherein:

FIG. 1 is a basic functional block diagram of a radio transceiverarchitecture, which can be used to facilitate an understanding of thepresent invention;

FIG. 2 is a block diagram of a conventional receiver section, which canbe used to implement the functions of the receiver section shown in FIG.1;

FIG. 3 is a block diagram of an image-rejection mixer stage that can beused for down-conversion with the receiver architecture illustrated inFIG. 1;

FIG. 4 is a schematic block diagram of a single chip transceiverarchitecture, which can be used to implement the apparatus and method ofthe present invention; and

FIG. 5 is a detailed circuit block diagram of a radio transceiver on asingle IC chip, in accordance with a second embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE DRAWINGS

The preferred embodiment of the present invention and its advantages arebest understood by referring to FIGS. 1–5 of the drawings, like numeralsbeing used for like and corresponding parts of the various drawings.

For the preferred embodiment, the air interface specification allowsdigital transmission of both voice and data. Such an air interface thatcan be used is described in commonly-assigned U.S. patent applicationSer. No. 08/685,069 to Dent, et al., filed Jul. 13, 1996, entitled“Shore-Range Radio Communications System And Method Of Use.” Thefrequency band that can be used is the unlicensed Industrial,Scientific, Medical (ISM) band at 2.4 GHz, which has 83.5 MHz bandwidthavailable for use. However, in the United States, the FederalCommunications Commission (FCC) requires frequency spreading foroperations where the transmitted power is higher than 0 dBm. There canbe numerous “interferers” or “jammers” operating in this band (e.g.,microwave ovens are notorious “interferers” in this band). Consequently,a frequency hopping scheme is used to provide increased immunity to suchinterference. Notably, in contrast to direct sequence frequencyspreading, the interference immunity provided by frequency hop spreadingis independent of the jammer's transmitted power.

In addition, with respect to the preferred embodiment, average frequencyspreading over the entire 83.5 MHz band results without having toprocess wide bandwidth signals. Although the frequency spectrum that theembodied transceiver can be operated in is wide enough to provide thespreading, the instantaneous bandwidth can be small, which allows thetransceiver's front end to be operated at a narrow band. In thepreferred system, the instantaneous (channel) bandwidth is 1 MHz,whereas the hopping is carried out in a pseudo-random way over 79 hopchannels (spanning 79 MHz). The preferred modulation scheme used isbinary Gaussian-shaped frequency shift keying (GFSK) This approachprovides a robust wireless communications link and allows the use ofrelatively simple transmitter and receiver circuitry.

For the preferred embodiment, the information signals are transmitted inpackets. Automatic Repeat Request (ARQ) error correction is employed tore-transmit packets received with errors in the data field. The voicefield is not re-transmitted, but the (robust) Continuous Variable SlopeDelta (CVSD) modulation scheme is used for speech coding. CVSD is a typeof adaptive delta modulation scheme whereby performance degradesgracefully in the presence of noise. A time-division duplex (TDD) schemeis used to achieve a full-duplex communications link. A duplex framelasts 1.25 ms, in which a packet is sent in one direction during thefirst 625 μs, and another packet is sent in the opposite directionduring the second 625 μs. Each transmission occurs at a new hopfrequency, which is determined by the user-dependent pseudo-random hopsequence.

In order to better understand the invention, it will be useful at thispoint to describe a radio transceiver in general terms. FIG. 1 is abasic functional block diagram of a radio transceiver architecture (10),which can be used to facilitate an understanding of the presentinvention. First considering the receiver section of the transceiver,due to requirements imposed based on antenna size and propagationconditions, the signals propagated over the air are normally conveyed byradio-frequency (RF) carriers. An RF signal received at the antenna (12)is frequency down-converted (14) to facilitate signal processing.Notably, the information being carried has a much lower rate than thecarrier frequency. Next, the down-converted signal is filtered (16), inorder to suppress all interference and noise outside the frequency bandof interest, and thus improve the receiver's signal-to-noise ratio. Thisprocess is commonly referred to as “channel filtering,” since only thechannel or frequency band of interest is filtered out.

Once the received signal has been channel filtered, the next step in theprocess is to recover the information (18) from the channel and convertit into a usable format. For example, the information recovered can bein the form of discrete symbols (e.g., data out) such as those used indigital modulation schemes, or an analog signal for audio or videoapplications. Notably, the key function of the receiver section is tofilter out the band of interest from the rest of the frequency spectrum.

The transmitter section of the transceiver (10) converts or shapes (20)the information to be transmitted into a signal format that can beconveyed by a carrier. That signal is then frequency upconverted (22) tothe desired high frequency (RF) band and transmitted from the antenna(12). Notably, for the transmitter section, the key function is toconfine the transmitted signal power to the band of interest (i.e., toleak as little signal power as possible to frequencies outside the bandof interest).

FIG. 2 is a block diagram of a conventional receiver section 30, whichcan be used to implement the functions of the receiver section shown inFIG. 1. Most conventional radio receivers employ a superheterodynereceiver architecture, such as the architecture of receiver section 30shown in FIG. 2. The received RF carrier from antenna 32 isdown-converted to a first intermediate frequency (IF) by mixing (34) theRF signal with a first local oscillator signal (36). A suitable bandpassfilter 38 (e.g., with sharp cut-off characteristics) is used for channelfiltering. The channel filtered signal is then down-converted to abaseband signal, by mixing (40) the filtered signal with a second localoscillator signal (42). At this point, additional filtering of thebaseband signal may be used. The information to be used (e.g., data) isthereby recovered (44).

One problem with integrating such a receiver on a chip deals withintegrating the IF bandpass filters (e.g., 38). For example, theperformance of a filter is determined by its quality (Q) factor. Q is ameasure of a filter's selectivity (how well it filters) and can berepresented by the expression: Q=f_(Q)/BW, where (f_(Q)) is the filter'scenter frequency, and BW is the filter's bandwidth. Therefore, a narrowfilter centered at a high frequency would have a high Q.

Generally, bandpass filters can be fabricated by a number of techniquesand integrated on semiconductor chips. However, the Q values achievablefor such filters are significantly limited using conventional electroniccomponents in silicon technology. The primary limiting factors are thelosses that occur between electronic components on the chip.

With respect to reducing interference and noise, only the bandwidth (BW)of the filter determines its performance in terms of signal-to-noiseratio. For a fixed bandwidth, low-Q filters can be integrated on a chipby lowering the center frequency, f_(Q). For the extreme case, f_(Q)becomes zero and the bandpass filter becomes a lowpass filter, which ismuch easier to integrate on chip than a bandpass filter. In this case,the signal being processed can be converted to baseband with only onedown-conversion step. Of course, this approach is attractive from anintegration standpoint and is indeed a way to obtain full integration.However, a second problem occurs with this approach, which is referredto as a “homodyne” or “zero-IF” architecture.

A so-called “DC offset” problem occurs with a zero-IF architecture,because the signal being processed is mapped directly to DC.Consequently, interference at DC is indistinguishable from the desiredsignal and cannot be filtered out. This problem also places morestringent requirements on the even order intermodulation characteristicsof the receiver. Part of the DC offset can be removed with additionalsignal processing, but this approach increases circuit complexity andthe power consumption of the IC.

An intermediate approach, which is suitable for integrating IF filterson a semiconductor chip, is to use a “low-IF” architecture. With thisapproach, the IF or filter's center frequency, f_(Q), is a relativelylow frequency, but not zero. This type of architecture allowsfabrication of a low Q filter which is suitable for integration on achip while avoiding DC problems.

Nevertheless, a third problem arises, which has to do with the imagecarrier. The process of mixing the received (RF) signal with a localoscillator carrier, f_(lo), produces a low IF signal, f_(Q), which notonly maps the frequency band of interest at f_(lo)+f_(Q), but also mapsthe image band at f_(lo)−f_(Q) to the IF signal (or vice versa) Thisprocess causes a significant problem, because after the two RF bands aremapped onto the same IF band, they are no longer distinguishable fromeach other. Therefore, an image-rejection device should be used.

FIG. 3 is a block diagram of an image-rejection mixer stage (50) thatcan be used for down-conversion with the receiver architectureillustrated in FIG. 1. Using such a stage, the received RF signal fromantenna 12 is coupled to a first and second mixer (52, 54). A localoscillator signal (56) is coupled directly to the first mixer (52), andalso phase-shifted 90 degrees (58) and coupled to the second mixer (54).The down-converted signal from the first mixer (52) is phase-shifted 90degrees (60) and algebraically added (62) to the phase-shifted,down-converted signal from the second mixer (54), which ultimatelyfunctions to suppress the image band.

The amount of image band suppression that can be realized with suchimage-rejection circuitry (e.g., FIG. 3) depends on how well the circuitcomponents can be matched, and depends on the frequency bandwidth overwhich suppression is desired. With on-chip components, a relatively highmatching accuracy should be attainable. Nevertheless, in practice, theimage rejection actually attainable for on-chip circuitry is somewhatlimited (e.g., about 30–40 dB for a 1 MHz bandwidth). However, inaccordance with the present invention (as described above with respectto the air interface), a frequency hopping system is employed in whicheach packet is transmitted in one of 79 available hop frequencies.Occasionally, interference such as a collision between packets can occurif two different users simultaneously occupy the same frequency hop.Consequently, with reduced image rejection performance, it follows thatdifferent users's packets occupying each other's image bands can alsointerfere with each other. In any event, for the preferred embodiment,such occasional packet collisions, whether resulting from to-channel,image-channel, or adjacent channel interference, are accounted andcompensated for in the air interface operations by employing anappropriate ARQ protocol for data transfers, and a robust speech codingformat (e.g., CVSD) for voice transfers. In other words, the presentinvention compensates for degraded receiver performance due to imageinterference, by the use of frequency hop spreading, error correction,and speech coding techniques specified for the air interface, whichallows full-integration of the receiver and (as described below)transmitter sections of the transceiver on a single IC chip.

Previously, when an attempt was made to place a transmitter and receiveron a single chip, one problem that occurred was that signals transmittedat relatively high power levels leaked into the receiver's input stage.In fact, such leakage or “cross-talk” has been a major design problem inprevious attempts to fabricate an entire transceiver on a chip. However,for the preferred embodiment of the invention, a TDD scheme is used forduplex operation over the air interface, which eliminates cross-talk andthereby facilitates full integration of the transceiver on a chip. Inother words, the transmitter and receiver sections of the embodiedtransceiver are not active simultaneously, and the problem of cross-talkor leakage from the transmitter to receiver in a fully integratedtransceiver is resolved.

Additionally, cross-talk or leakage can be reduced further by employingdifferent transmit and receive frequencies using a frequency-divisionduplex (FDD) scheme. Normally, the use of an FDD scheme would require aduplexer at the transceiver's antenna stage in order to separate thetransmitted and received signals. However, by also employing a TDDscheme in accordance with the invention, such a duplexer is not needed.Moreover, to further reduce the number of components on the chip, asingle variable controlled oscillator (VCO) is used in the preferredembodiment, alternately for up-conversion in the transmit section anddown-conversion in the receive section.

FIG. 4 is a schematic block diagram of a single chip transceiverarchitecture, which can be used to implement the apparatus and method ofthe present invention. For the preferred embodiment, binary FSK shapedwith a Gaussian filter is the modulation scheme used. Specifically, theuse of FSK modulation for a single chip transceiver has a number ofimplementation advantages. For example, the detection function iscarried out directly at the IF with a frequency modulation (FM)discriminator stage (122). This approach eliminates the need for asecond down-conversion to baseband stage for information recovery. Next,the transmit section is simplified so chat the information symbols to betransmitted can be coupled directly to a VCO (e.g., HF oscillator 118),which converts these symbols to an FM signal. With this approach, asingle VCO is sufficient for the transmit section, and the need for aseparate up-conversion mixer is eliminated. Yet another advantage ofusing FSK is that the non-coherent detection of FSK signals isrelatively insensitive to frequency errors. In this case, a frequencyerror shows up as a DC offset signal at the output of the FM detector.However, an automatic frequency control (AFC) stage can be used toquickly compensate for the offset. This approach eliminates the need forhighly stable local oscillator stages or accurate frequency trackingschemes.

Still another advantage of FSK modulation is that the received signalcan be hard-limited after channel filtering. The information beingreceived is contained only in the phase and not in the amplitude of thesignal. Consequently, this approach eliminates the need for awkwardautomatic gain control (AGC) circuitry and amplitude tracking schemes.The AGC operation would also be severely hindered by the frequencyhopping defined in the air interface due to the un-correlated signalfading on the different hop frequencies.

Returning to FIG. 4, by making appropriate adjustments in the airinterface (as described above) to compensate for implementation problemsencountered with others' previous attempts to integrate an entiretransceiver on a single IC chip, the relatively simple architectureshown in FIG. 4 can be used (in accordance with the present invention).In comparison with the architecture disclosed in FIG. 1, the basicblocks of FIG. 1 are still recognizable. Notably. each basic block shownin FIG. 1 can be replaced by only one circuit in the architecture shownin FIG. 4. For example, in FIG. 4, the down-conversion step is performedin the image-rejection mixer (116), which converts the signal from RF toa low IF. A bandpass filter (120), which is selective at this low IF,performs the channel selection. This channel filtered signal is thenrecovered in an FM discriminator (122). Notably, no seconddown-conversion step to a lower IF or baseband frequency is required,since the FM discriminator (122) can detect the received signal directlyat the low IF.

In the transmitter section of FIG. 4, the signal to be transmitted isshaped with a Gaussian shaping filter (124) in order to suppress theout-of-band signal power. The shaped signal is coupled directly to a VCO(118), which generates the FM signal directly at the desired RF.Notably, only a single VCO is needed for the entire transceiver. Thissame VCO (118) performs the down-conversion function during the receivecycle, and the up-conversion function during the transmit cycle. Thelow-IF used is selected at an appropriate frequency, in order to allowon-chip integration of a bandpass filter (120) with sufficientselectivity. For the preferred embodiment, a 3 MHz IF (f_(Q)) is used,which allows implementation of a CMOS gyrator filter (on chip) with abandwidth of 1 MHz and, thus, a Q of 3. The low-pass shaping filter(124) and a low-pass detection filter (not explicitly shown) subsequentto the FM discriminator can be implemented in a similar way. The FMdetector (122) is preferably fabricated as a quadrature detector. Forthe VCO stage (118), bond-wire inductors are used as resonators in theoscillator tank, without external (off-chip) components. Preferably, allfilters are tuned with a common reference circuit to compensate forfabrication tolerances.

FIG. 5 is a detailed circuit block diagram of a short-range radiotransceiver mounted on a single IC chip, in accordance with a secondembodiment of the present invention. However, although the radiotransceiver shown is described with respect to a single IC chipimplementation, this description is for illustrative purposes only andthe present invention is not intended to be so limited. For example,some of the components shown in FIG. 5 may be located external to the ICchip. Returning to FIG. 5, the transceiver on a chip (200) includes atransmit/receive antenna 202 coupled to a low noise amplifier (LNA) 204in the receiver front end. The output of the LNA is coupled to animage-rejection mixer, which is composed of a first mixer 206 for the Ichannel, a second mixer 208 for the Q channel, a 45 degree phase shifter210, a 135 degree phase shifter 212, a 90 degree phase shifter 214, anda combiner 216. A local oscillator signal is coupled to the 90 degreephase shifter 214 from a VCO 218. Consequently, image rejection isaccomplished by recombining the phase shifted IF I and Q signals toproduce an output IF signal from the combiner 216.

For this embodiment, the IF signal selected is about 3.0 MHz. The IFsignal output from the combiner 216 is coupled to the IF receivercircuitry, which includes a bandpass is filter 220 to suppress signalson adjacent channels. The bandpass filter is preferably a stagger-tunedIF filter using transconductance-C type filtering. The IF receivercircuitry also includes a hard limiter (H.L.) 222, an FM discriminator224, and a lowpass filter 226. The IF receiver circuitry can alsoinclude an RSSI indicator with an A/D converter (not explicitly shown).The IF signal is detected (224), and the information recovered is outputfrom the lowpass filter 226.

Transceiver 200 on a chip also includes a phase locked loop, which iscomposed of a phase detector 230, loop filter 236, and a prescaler withmodulus logic 240. The phase locked loop is a component of a synthesizerincluding the phase detector 230, charge pump 232, regulator filter 234,loop filter 236, prescaler 240, modulus logic circuitry 238, VCO 218,and a buffer 219. As such, the input information signal (e.g., data in),shaped by the shaping filter 256, is used to directly modulate the VCO.A sample-and-hold (S/H) circuit (not explicitly shown) stabilizes theinput voltage to the VCO, while the VCO is being directly modulated. TheVCO 218 is also a component of the transmitter section. Fortransmissions, the output of the VCO 218 is coupled to a power amplifier242 and to the antenna 202.

Fully differential signal paths are used to suppress common-mode noiseand interference signals. In addition, all receive filters, transmitfilters, and the FM discriminator apply matched electronic circuits.Autotuning of all the filters and the discriminator is provided by areference filter which is locked to the crystal oscillator 248.

The transceiver 200 also includes digital circuitry 244 to provide powerdown control, programming of certain analog blocks on the chip due toprocess variations, and synthesizer control logic. The digital circuitry244 is connected to a serial digital interface connection 246. A numberof typical functional circuit blocks are also included on the chip, suchas, for example, a crystal oscillator (XO) 248, frequency adjustable lowpower oscillator (LPO), power-on-reset (POR) 252, and finite statemachine (FSM) 254. Consequently, the one chip transceiver shown in FIG.5 includes power down logic for all analog circuit blocks, logic to tunethe analog circuit blocks, a serial-to-parallel converter, and decodinglogic.

In summary, as illustrated by the embodiments shown in FIGS. 4 and 5, anentire radio transceiver is completely integrated into one IC chip. Inorder to integrate the IF filters on the chip, a heterodyne architecturewith a relatively low IF is used. A single directly modulated VCO isused for both up-conversion and down-conversion, and bond-wires are usedas resonators in the oscillator tank for the VCO. A TDD scheme is usedin the air interface to eliminate cross-talk or leakage. AGaussian-shaped binary FSK modulation scheme is used to provide a numberof other implementation advantages (as described above).

Although a preferred embodiment of the method and apparatus of thepresent invention has been illustrated in the accompanying Drawings anddescribed in the foregoing Detailed Description, it will be understoodthat the invention is not limited to the embodiments disclosed, but iscapable of numerous rearrangements, modifications and substitutionswithout departing from the spirit of the invention as set forth anddefined by the following claims.

1. A radio for transmitting and receiving, via an antenna, a pluralityof high-frequency signals in a time-division-duplex mode on a single ICchip, the radio comprising: a circuit path adapted to connect theantenna to a data output port and to a data input port, wherein thecircuit path comprises: (1) a down-conversion section fordown-converting received high-frequency signals of the plurality ofhigh-frequency signals; (2) a bandpass filter for filtering signalsderived from the received high-frequency signals; (3) a detector fordetecting a received data signal from a received filtered signal,wherein the received data signal is sent to the data output port; and(4) an up conversion section for up converting an information signalreceived from the data input port to a high-frequency signal of theplurality of high-frequency signals; wherein the circuit path comprisingthe bandpass filter, the detector, the up conversion section, and thedown-conversion section is integrated into the single IC chip; whereinbandpass filtering operations are performed by components integratedinto the single IC chip; and automatic re-transmission request errorcorrection means for data transfer.
 2. The radio of claim 1, wherein theup conversion section comprises a variable controlled oscillator.
 3. Theradio of claim 1, wherein the up conversion section comprises a directlymodulated variable controlled oscillator.
 4. The radio of claim 1,wherein the radio comprises an image-rejection-mixer stage.
 5. The radioof claim 1, further comprising autotuning means for autotuning aplurality of filters and the detector.
 6. The radio of claim 1, furthercomprising a digital power-down control circuit to provide power-downcontrol for the radio, wherein the power-down control circuit isintegrated into the single IC chip.
 7. The radio of claim 1, furthercomprising a low-power oscillator integrated into the single IC chip. 8.The radio of claim 1, wherein the signals derived from the receivedhigh-frequency signals of the plurality of high-frequency signals arelow intermediate frequency signals.
 9. The radio of claim 1, wherein thecircuit path further comprises a low-pass filter for filtering thereceived data signal output by the detector and the low-pass filter isconnected to the detector and the data output port.
 10. The radio ofclaim 1, further comprising the antenna.
 11. A radio for transmittingand receiving, via an antenna, a plurality of high-frequency signals ina time-division-duplex mode on a single IC chip, the radio comprising: acircuit path adapted to connect the antenna to a data output port and toa data input port, wherein the circuit path comprises: (1) a bandpassfilter for filtering signals derived from the received high-frequencysignals; (2) a detector for detecting a received data signal from areceived filtered signal, wherein the received data signal is sent tothe data output port; and (3) an up conversion section for up convertingan information signal received from the data input port to ahigh-frequency signal of the plurality of high-frequency signals; (4) ashaping filter connected to an input of the up-conversion section;wherein the circuit path comprising the bandpass filter, the detector,the up conversion section, and the shaping filter is integrated into thesingle IC chip; and wherein bandpass filtering operations are performedby components integrated into the single IC chip; and automaticre-transmission request error correction means for data transfer. 12.The radio of claim 11, wherein the up conversion section comprises avariable controlled oscillator.
 13. The radio of claim 11, wherein theup conversion section comprises a directly modulated variable controlledoscillator.
 14. The radio of claim 11, wherein the radio comprises animage-rejection-mixer stage.
 15. The radio of claim 11, furthercomprising autotuning means for autotuning a plurality of filters andthe detector.
 16. The radio of claim 11, further comprising a digitalpower-down control circuit to provide power-down control for the radio,wherein the power-down control circuit is integrated into the single ICchip.
 17. The radio of claim 11, further comprising a low-poweroscillator integrated into the single IC chip.
 18. The radio of claim11, wherein the signals derived from the received high-frequency signalsof the plurality of high-frequency signals are low intermediatefrequency signals.
 19. The radio of claim 11, wherein the circuit pathfurther comprises a low-pass filter for filtering the received datasignal output by the detector and the low-pass filter is connected tothe detector and the data output port.
 20. The radio of claim 11,further comprising the antenna.